FemtoClock NG Octal Universal 8T49N286 Frequency Translator Datasheet Description The 8T49N286 has two independent, fractional-feedback PLLs that SyncE (G.8262) applications can be used as jitter attenuators and frequency translators. It is Wireless base station baseband equipped with six integer and two fractional output dividers, allowing Data communications the generation of up to eight different output frequencies, ranging 100G Ethernet from 8kHz to 1GHz. Four of these frequencies are completely independent of each other and the inputs. The other four are related Features frequencies. The eight outputs may select among LVPECL, LVDS, HCSL or LVCMOS output levels. Supports SDH/SONET and Synchronous Ethernet clocks including all FEC rate conversions This functionality makes it ideal to be used in any frequency <0.3ps RMS Typical Jitter (including spurs), 12kHz to 20MHz translation application, including 1G, 10G, 40G and 100G Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T Operating modes: locked to input signal, holdover and free-run G.709 (2009) FEC rates. The device may also behave as a frequency Initial holdover accuracy of 50ppb synthesizer. Accepts up to four LVPECL, LVDS, LVHSTL, HCSL or LVCMOS The 8T49N286 accepts up to four differential or single-ended input input clocks clocks and a crystal input. Each of the two internal PLLs can lock to Accepts frequencies ranging from 8kHz up to 875MHz different input clocks which may be of independent frequencies. The Auto and manual input clock selection with hitless switching other two input clocks are intended for redundant backup of the Clock input monitoring, including support for gapped clocks primary clocks and must be related in frequency to their primary. Phase-Slope Limiting and Fully Hitless Switching options to The device supports hitless reference switching between input control output phase transients clocks. The device monitors all input clocks for Loss of Signal (LOS), Operates from a 10MHz to 40MHz fundamental-mode crystal and generates an alarm when an input clock failure is detected. Generates 8 LVPECL / LVDS / HCSL or 16 LVCMOS output Automatic and manual hitless reference switching options are clocks supported. LOS behavior can be set to support gapped or ungapped Output frequencies ranging from 8kHz up to 1.0GHz (diff) clocks. Output frequencies ranging from 8kHz to 250MHz (LVCMOS) The 8T49N286 supports holdover for each PLL. The holdover has an initial accuracy of 50ppB from the point where the loss of all Eight General Purpose I/O pins with optional support for status and control applicable input reference(s) has been detected. It maintains a historical average operating point for each PLL that may be returned Eight Output Enable control inputs to in holdover at a limited phase slope. Lock, Holdover and Loss-of-Signal status outputs The device places no constraints on input to output frequency Open-drain Interrupt pin conversion, supporting all FEC rates, including the new revision of Write-protect pin to prevent configuration registers being altered ITU-T Recommendation G.709 (2009), most with 0ppm conversion Nine programmable loop bandwidth settings for each PLL from error. 1.4Hz to 360Hz. Each PLL has a register-selectable loop bandwidth from 1.4Hz to Optional Fast Lock function 360Hz. Programmable output phase delays in steps as small as 16ps Each output supports individual phase delay settings to allow 2 2 Register programmable through I C / SPI or via external I C output-output alignment. EEPROM The device supports Output Enable inputs and Lock, Holdover and Bypass clock paths for system tests LOS status outputs. Power supply modes: 2 The device is programmable through an I C interface. It also supports V / V / V CC CCA CCO 2 I C master capability to allow the register configuration to be read 3.3V / 3.3V / 3.3V 3.3V / 3.3V / 2.5V from an external EEPROM. The user may select whether the 2 3.3V / 3.3V / 1.8V (LVCMOS) programming interface uses I C protocols or SPI protocols, however 2.5V / 2.5V / 3.3V in SPI mode, read from the external EEPROM is not supported. 2.5V / 2.5V / 2.5V 2.5V / 2.5V / 1.8V (LVCMOS) Typical Applications -40C to 85C ambient operating temperature OTN or SONET / SDH equipment Line cards (up to OC-192, and Package: 72QFN, lead-free RoHs (6) supporting FEC ratios) OTN de-mapping (Gapped Clock and DCO mode) Gigabit and Terabit IP switches / routers including support of Synchronous Ethernet 2020 Renesas Electronics Corporation. 1 October 28, 20208T49N286 Datasheet 8T49N286 Block Diagram IntN Output Q0 Divider Fractional Feedback XTAL APLL 0 IntN Output OSC Q1 Divider Lock 0 Input Clock Holdover 0 Monitoring, FracN Output CLK0 P0 Priority, Q2 Divider Fractional & CLK1 P1 Feedback Selection APLL 1 FracN Output CLK2 P2 Q3 Divider Lock 1 CLK3 P3 Holdover 1 IntN Q4 Reset nRST IntN LOS Q5 Logic Status Registers GPIO OTP Logic 2 I C Master IntN Q6 Control Registers SCLK/SCLK 8 2 SDATA/SDO I C/ SPI Slave IntN Q7 2 Serial (I C) EEPROM nINT PLL BYP GPIO nWP S A0/nCS, S A1/SDI Figure 1. 8T49N286 Functional Block Diagram 2020 Renesas Electronics Corporation. 2 October 28, 2020