FemtoClock NG Jitter Attenuator and 8V19N407 Clock Synthesizer DATA SHEET General Description Features 8V19N407 is a fully integrated FemtoClock NG Jitter Attenuator Core timing unit for JESD204B wireless infrastructure clocks and Clock Synthesizer. The device is a high-performance clock Fourth generation FemtoClock NG technology solution for conditioning and frequency/phase management of First stage PLL uses an external VCXO for jitter attenuation wireless base station radio equipment boards and is optimized to Second PLL stage facilitates an integrated VCO for frequency deliver excellent phase noise performance. The device supports synthesis JESD204B subclass 0 and 1 clock implementations. The device is 8V19N407-19: f = 1900 - 2000MHz very flexible in programming of the output frequency and phase. A VCO 8V19N407-24: f = 2400 - 2500MHz two-stage PLL architecture supports both jitter attenuation and VCO frequency multiplication. The first stage PLL is the jitter attenuator Five differential configurable LVPECL, LVDS clock outputs with a and uses an external VCXO for best possible phase noise variable output amplitude characteristics.The second stage PLL lock on the VCXO-PLL output Four differential LVDS system reference (SYSREF) signal outputs signal and synthesizes the target frequency. The second-stage PLL Synchronization between clock and system reference signals use an internal VCO. Wide input frequency range supported by 8-bit pre- and 15-bit The device supports the clock generation of high-frequency clocks VCXO-PLL feedback divider from the VCO and low-frequency system reference signals Output clock frequencies: f N VCO (SYSREF). The system reference signals are internally Three independent output clock frequency dividers N (range of 1 synchronized to the clock signals. Delay functions exist for achieving to 96) alignment and controlled phase delay between system reference Phase delay capabilities for alignment/delay for clock and and clock signals and to align/delay individual output signals. The SYSREF signals input is monitored for activity. The hold-over is provided to handle clock input failure scenarios. Auto-lock, individually programmable Individual output phase adjustment (Clock): one-period of the output frequency dividers and phase adjustment capabilities are selected VCO frequency in 64 steps added for flexibility. The device is configured through a 4-wire SP Individual output phase adjustment (SYSREF): approximately serial interface and reports lock and signal loss status in internal half-period of the selected VCO frequency in 8 steps registers and optionally via an lock detect (nINT) output. The device Internal, SPI controlled SYSREF pulse generation is packaged in a lead-free (RoHS 6) 72-lead VFQFN package. The SYSREF frequencies: f N VCO S extended temperature range supports wireless infrastructure, SYSREF frequency dividers N : 64 to 2048 (10 dividers) telecommunication and networking end equipment requirements. S Clock input compatible with LVPECL, LVDS and LVCMOS signals The device is a member of the high-performance clock family from IDT. Dedicated power-down features for reducing power consumption Input clock monitoring Holdover for temporary loss of input signal scenarios Support of output power-down and output disable Typical clock output phase noise at 614.4MHz: 1kHz offset: -122.3 dBc/Hz 10kHz offset: -123.6 dBc/Hz 100kHz offset: -128.3 dBc/Hz 1MHz offset: -149.4 dBc/Hz 10MHz offset: -155.6 dBc/Hz RMS phase noise of 614.4 MHz clock (12kHz - 20MHz): <100fs (typical) Status conditions with programmable functionality for loss-of-lock and loss of reference indication Lock detect (nINT) output for status change indication LVCMOS/LVTTL compatible SPI serial interface 3.3V core and output supply mode Supports 3.3V I/O logic levels for all control pins -40C to +85C ambient operating temperature Lead-free (RoHS 6) 72-lead VFQFN package REVISION 2 10/1/15 1 2015 INTEGRATED DEVICE TECHNOLOGY, INC.8V19N407 DATA SHEET Block Diagram C C 01 02 R f 0 VCXO C C V0 V1 R V nVCXO LFV VCXO QVCXO nQVCXO VCXO-PLL FemtoClock NG C 1 CLK Clock PFD CR 0 F P V Monitor VCO nCLK PFD V 8 Bit BYPASS M V 15 Bit M F 8 Bit Holdover Control QCLKA0 nQCLKA0 CLK A SYSREF QCLKA1 N N S A Control A nQCLKA1 Delay Divider 0 QREFA0 QREF MUX A0 1 nQREFA0 A0 0 QREFA1 QREF MUX A1 nQREFA1 1 A1 QCLKB0 nQCLKB0 CLK B QCLKB1 N B B nQCLKB1 SPICLK SPI Slave Register File Delay Divider 0 MOSI Controller QREFB0 QREF MUX B0 1 MISO nQREFB0 B0 nLE 0 nINT QREFB1 QREF MUX B1 SELSV 1 nQREFB1 B1 CLK C QCLKC N C C nQCLKC Delay Divider 8V19N407 REVISION 2 10/1/15 2 FEMTOCLOCK NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER VCOR VCO LF