Ethernet PLL and IEEE 1588 Synthesizer Short Form Datasheet IDT8V89316 for Industrial Automation and Power Internal DCO has resolution of 0.01105 ppb and can be controlled FEATURES by an external processor via I2C interface for IEEE 1588 clock gen- HIGHLIGHTS eration Digital PLL locks to Ethernet physical layer clocks One Analog PLL for jitter attenuation Provides clocks for 1 Gigabit Ethernet and QSGMII IN1, IN2 and IN3 accept single ended reference clocks whose fre- Internal Digitally Controlled Oscillator supports IEEE 1588 clock quencies can be 25 MHz, 125 MHz or 156.25 MHz generation OUT1 outputs a differential clock with frequency of 125 MHz or Jitter generation <0.65 ps RMS (10 kHz to 20 MHz) meets jitter 156.25 MHz requirements of 1 GbE PHYs and QSGMII OUT2 to OUT6 output differential clocks all with the same fre- quency of 125 MHz or 156.25 MHz MAIN FEATURES OUT7 outputs a free-running LVCMOS clock with frequency of 25 Digital PLL synchronizes with Ethernet connected synchronization MHz sources DPLL bandwidth of 1.2 Hz OTHER FEATURES DPLL holdover accuracy is 1.1X10-5 ppm and instantaneous hold- I2C microprocessor interface mode over accuracy is 4.4X10-8 ppm IEEE 1149.1 JTAG Boundary Scan Input references are monitored for frequency offset and activity Single 3.3 V operation with 5 V tolerant CMOS I/Os DPLL holdover, free run and hitless reference switching can be 1mm ball pitch CABGA green package forced by the host processor or can be automatically controlled by APPLICATIONS an internal state machine Industrial Automation Power Systems Crystal Monitors IN1 Input Pre-Divider Priority IN2 Input Pre-Divider Priority Input Pre-Divider Priority IN3 OUT1 POS Divider OUT1 NEG Input DPLL/ Selector DCO APLL OUT2 POS Divider OUT2 NEG OUT3 POS OUT3 NEG I2C Microprocessor Interface OUT4 POS IN APLL POS OUT4 NEG IN APLL NEG OUT5 POS OUT5 NEG OUT6 POS JTAG OUT6 NEG OUT7 APLL OSCI Figure 1. Functional Block Diagram IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. TM IEEE 1588 is a trademark of its respective owner 1 May 5, 2014 IDT CONFIDENTIALIDT8V89316 DATASHEET ETHERNET PLL AND IEEE 1588 SYNTHESIZER FOR INDUSTRIAL AUTOMATION AND POWER SYSTEMS DESCRIPTION The IDT8V89316 Ethernet PLL for Industrial Automation and Power control loop is opened and the DCO can be used by an algorithm Systems is used to synchronize equipment with synchronization sources (e.g. IEEE 1588 clock servo) running on an external processor to syn- using the Ethernet physical layer it can also be used by external IEEE thesize clock signals. 1588 clock recovery servos to synthesize IEEE 1588 clocks. The The IDT8V89316 requires a 12.8 MHz master clock for its reference IDT8V89316 low jitter output clocks can be used to directly synchronize monitors and other digital circuitry. The frequency accuracy of the mas- 1 Gigabit Ethernet PHYs and QSGMII devices. ter clock determines the frequency accuracy of the DPLL in Free-Run The IDT8V89316 synchronization functions are provided by a Digital mode. The frequency stability of the master clock determines the fre- PLL (DPLL) with an embedded clock synthesizer. The DPLL accepts quency stability of the DPLL in Free-Run mode and in Holdover mode. three single ended reference inputs that can operate at 25 MHz, 125 Refer to the IDT application note Recommended Crystal Oscillators for TM MHz or 156.25 MHz. The references are continually monitored for loss IDTs Network Synchronization WAN-PLL for guidance. of signal and for frequency offset per user programmed thresholds. The The clock synthesized by the IDT8V89316 DPLL is passed through a active reference for the DPLL is determined by forced selection or by voltage controlled crystal oscillator (VCXO) based jitter attenuating ana- automatic selection based on user programmed priorities and locking log PLL (APLL). The APLL drives independent dividers that have differ- allowances and based on the reference monitors. ential outputs. The APLL uses an external crystal resonator with The DPLL supports four primary operating modes: Free-Run, resonant frequencies equal to the APLL base frequency divided by 25. Locked, Holdover and Digitally Controlled Oscillator (DCO) Control. In The output clocks generated by the APLL exhibits jitter below 0.65ps Free-Run mode the DPLL generates a clock based on the master clock RMS over the integration range 10 kHz to 20 MHz. alone. In Locked mode the DPLL filters reference clock jitter with the The IDT8V89316 generates a 25MHz single ended output that is selected bandwidth. In Locked mode the long-term DPLL frequency based on the free running 12.8 MHz master clock. The frequency accu- accuracy is the same as the long term frequency accuracy of the racy and the frequency stability of this 25 MHz clock are determined by selected input reference. In Holdover mode the DPLL uses frequency the master clock. data acquired while in Locked mode to generate accurate frequencies when input references are not available. In DCO Control Mode the DPLL Description 2 May 5, 2014 IDT CONFIDENTIAL