Datasheet RC32504A FemtoClock 2 Sub-100fs Universal Frequency Translator The RC32504A is a small, low-power timing 4 differential/8 LVCMOS outputs component designed to be placed immediately Any frequency from 10MHz to 1GHz (180MHz for adjacent to a PHY, switch, ASIC or FPGA that LVCMOS) requires several reference clocks with jitter Programmable output buffer supports HCSL performance less than 100fs. The RC32504A can act (DC-coupled), LVDS/LVPECL/CML (AC-coupled) as a frequency synthesizer to locally generate the or two LVCMOS reference clock, a jitter attenuator to perform local clean-up and/or frequency translation of a Differential output swing is selectable: 400mV to centrally-supplied reference, a Synchronous Ethernet 800mV equipment clock to perform passband filtering and Output Enable input with programmable effect clean-up of network-supplied references or as a DCO 2 Supports up to 1MHz I C or up to 20MHz SPI serial for frequency margining or OTN clock applications. processor port The device is a member of the Renesas Can configure itself automatically after reset high-performance FemtoClock2 family. through internal customer-definable One-Time Features Programmable (OTP) memory with up to four different configurations Jitter below 100fs RMS (10kHz to 20MHz) 4 4 mm 24-QFN package Compliant with ITU-T G.8262 for synchronous Ethernet/OTN (EEC/OEC) and ITU-T G.8262.1 for Applications enhanced synchronous Ethernet/OTN Synchronous Ethernet/OTN equipment (eEEC/eOEC) Reference clock generator for 100Gbps/400Gbps PLL core consists of fractional-feedback Analog PHYs or switches PLL (APLL) which can optionally be steered by a Digital PLL (DPLL) Adjustable OTN clock reference for OTU3/OTU4 mappers Operates from a 25MHz to 80MHz crystal or XO Reference clock for programmable FiberOptic APLL frequency independent of input/crystal Modules frequency Operates as a frequency synthesizer, jitter Block Diagram attenuator, synchronous equipment slave clock or Digitally Controlled Oscillator (DCO) /RFN HWHFW /2&. DPLL loop filter programmable from 0.1Hz to 2XW 287 12kHz LY 7 / )U DF1 2VF 2 3// DCO has tuning granularity of < 1ppt 2XW 287 ,1 Programmable input buffer supports HCSL, LVDS, LY LJLWDO or two LVCMOS with no external terminations &/.,1 3// needed ,1 2XW 287 LY Input frequencies: 1MHz to 800MHz (250MHz for , & 63, 273 LVCMOS) 2XW 287 LY 6(/ Reference monitor qualifies/disqualifies input clock 2( Programmable status output R31DS0044EU0103 Rev.1.03 Page 1 Nov 3, 2021 2021 Renesas Electronics LVWHUV 5HJRC32504A Datasheet Contents 1. About this Document 9 1.1 Document Conventions 9 1.1.1 Signal Notation . 9 1.1.2 Object Size Notation . 9 1.1.3 Numeric Notation 9 1.1.4 Endianness 9 2. Pin Information 10 2.1 Pin Assignments 10 2.2 Pin Descriptions 10 3. Specifications . 13 3.1 Absolute Maximum Ratings 13 3.2 Recommended Operating Conditions 13 3.3 Reference Clock Phase Jitter and Phase Noise 14 3.4 AC Electrical Characteristics . 17 3.5 DC Electrical Characteristics . 21 4. Applications Information 28 4.1 Power Considerations 28 4.2 Recommendations for Unused Input and Output Pins . 28 4.2.1 CLKIN/nCLKIN Input 28 4.2.2 LVCMOS Control Pins . 28 4.2.3 LVCMOS Outputs 28 4.2.4 Differential Outputs . 28 4.3 Clock Input Interface . 28 4.4 Crystal Recommendation . 29 4.5 Overdriving the XTAL Interface . 30 4.6 Differential Output Termination . 31 4.6.1 Direct-Coupled HCSL Termination 31 4.6.2 Direct-Coupled LVDS Termination 32 4.6.3 AC-Coupled Differential Termination 32 5. Architecture . 33 5.1 Modes of Operation 33 5.1.1 Frequency Synthesizer/Digitally Controlled Oscillator (DCO) . 33 5.1.2 Jitter Attenuator/SyncE 34 6. Blocks . 35 6.1 Device Reset Logic 35 6.1.1 Bias Calibration 35 6.2 Crystal Oscillator 35 6.3 Reference Clock Input 35 6.4 Analog Phase Lock Loop . 35 6.4.1 Frequency Doubler . 35 6.4.2 APLL Loop Filter (LPF) 36 6.4.3 Voltage-Controlled Oscillator (VCO) 36 6.4.4 APLL Feedback Divider 36 6.4.5 APLL Lock Detector . 36 6.4.6 Direct DCO Control . 36 R31DS0044EU0103 Rev.1.03 Page 2 Nov 3, 2021