CY28346 CY28346 Clock Synthesizer with Differential CPU Outputs 5/6 copies of 3V66 clocks Features SMBus support with read-back capabilities Compliant with Intel CK 408 Mobile Clock Synthesizer Spread Spectrum electromagnetic interference (EMI) specifications reduction 3.3V power supply Dial-a-Frequency features Three differential CPU clocks Dial-a-dB features Ten copies of PCI clocks 56-pin TSSOP and SSOP packages 1 Table 1. Frequency Table 66BUFF(0:2)/ USB/ S2 S1 S0 CPU (0:2) 3V66 3V66(0:4) 66IN/3V665 PCI FPCI REF DOT 1 0 0 66M 66M 66IN 66-MHz clock input 66IN/2 14.318M 48M 1 0 1 100M 66M 66IN 66-MHz clock input 66IN/2 14.318M 48M 1 1 0 200M 66M 66IN 66-MHz clock input 66IN/2 14.318M 48M 1 1 1 133M 66M 66IN 66-MHZ clock input 66IN/2 14.318M 48M 0 0 0 66M 66M 66M 66M 33 M 14.318M 48M 0 0 1 100M 66M 66M 66M 33 M 14.318M 48M 0 1 0 200M 66M 66M 66M 33 M 14.318M 48M 0 1 1 133M 66M 66M 66M 33 M 14.318M 48M M 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z M 0 1 TCLK/2 TCLK/4 TCLK/4 TCLK/4 TCLK/8 TCLK TCLK/2 Block Diagram Pin Configuration VDD 1 56 REF XIN REF XIN 2 55 S1 XOUT 3 54 S0 XOUT 4 53 CPU STP VSS CPUT(0:2) PLL1 5 52 CPUT0 PCIF0 CPUC(0:2) PCIF1 6 51 CPUC0 PCIF2 7 50 VDD CPU STP 8 49 CPUT1 VDD IREF 9 48 CPUC1 VSS VSSIREF 10 47 VSS PCI0 3V66 0 S(0:2) PCI1 11 46 VDD PCI2 12 45 CPUT2 3V66 1/VCH MULT0 13 44 CPUC2 PCI3 14 43 MULT0 VDD VTT PG /2 PCI(0:6) 15 42 IREF VSS PCI4 16 41 VSSIREF PCI STP PCI F(0:2) PCI5 17 40 S2 18 39 48MUSB PLL2 PCI6 48M USB 19 38 48MDOT VDD 48M DOT 20 37 VDD VSS 66B0/3V66 2 21 36 VSS WD PD 66B1/3V66 3 22 35 3V66 1/VCH Logic 23 34 PCI STP 66B2/3V66 4 I2C 24 33 3V66 0 SDATA 66IN/3V66 5 25 32 VDD SCLK Logic PD VDDA 26 31 VSS 66B 0:2 /3V66 2:4 VSSA 27 30 SCLK Power VDDA 29 66IN/3V66-5 VTT PG 28 SDATA Up Logic Note: 1. TCLK is a test clock driven on the XTAL IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, a 0 state will be latched into the devices internal state register.......................Document : 38-07331 Rev. *C Page 1 of 19 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com CY28346 Pin Description Pin Name PWR I/O Description 2XIN I Oscillator Buffer Input. Connect to a crystal or to an external clock. 3XOUT V O Oscillator Buffer Output. Connect to a crystal. Do not connect when an external DD clock is applied at X . IN 52, 51, 49, 48, CPUT(0:2), V O Differential Host Output Clock Pairs. See Table 1 for frequency/functionality. DD 45, 44 CPUC(0:2) 10, 11, 12, 13, PCI(0:6) V O PCI Clock Outputs. Are synchronous to 66IN or 3V66 clock. See Table 1. DDP 16, 17, 18 5, 6, 7 PCIF (0:2) V O 33MHz PCI Clocks. 2 copies of 66IN or 3V66 clocks that may be free running DD (not stopped when PCI STP is asserted LOW) or may be stoppable depending on the programming of SMBus register Byte3,Bits (3:5). 56 REF V O Buffered Output Copy of the Devices X Clock. DD IN 42 IREF V I Current Reference Programming Input for CPU Buffers. A resistor is DD connected between this pin and VSSIREF. 28 VTT PG V I Qualifying Input that Latches S(0:2) and MULT0. When this input is at a logic DD LOW, the S(0:2) and MULT0 are latched. 39 48MUSB V O Fixed 48 MHz USB Clock Outputs. DD48 38 48MDOT V O Fixed 48 MHZ DOT Clock Outputs. DD48 33 3V66 0 V O 3.3V 66 MHz Fixed-frequency Clock. DD 35 3V66 1/VCH V O 3.3V Clock Selectable with SMBus Byte0,Bit5, When Byte5,Bit5. When Byte DD 0,Bit 5 is at a logic 1, then this pin is a 48M output clock. When Byte0,Bit5 is a logic 0, this is a 66M output clock (default). 25 PD V I Power-down Mode Pin. A logic LOW level causes the device to enter a DD PU power-down state. All internal logic is turned off except for the SMBus logic. All output buffers are stopped. 43 MULT0 I Programming Input Selection for CPU Clock Current Multiplier. PU 55, 54 S(0,1) I I Frequency Select Inputs. See Table 1. 29 SDATA I I Serial Data Input. Conforms to the SMBus specification of a Slave Receive/Transmit device. It is an input when receiving data. It is an open drain output when acknowledging or transmitting data. 30 SCLK I I Serial Clock Input. Conforms to the SMBus specification. 40 S2 V I Frequency Select Input. See Table 1. This is a Tri-level input which is driven DD T HIGH, LOW or driven to a intermediate level. 34 PCI STP V I PCI Clock Disable Input. When asserted LOW, PCI (0:6) clocks are synchro- DD PU nously disabled in a LOW state. This pin does not effect PCIF (0:2) clocks outputs if they are programmed to be PCIF clocks via the devices SMBus interface. 53 CPU STP V I CPU Clock Disable Input. When asserted LOW, CPUT (0:2) clocks are DD PU synchronously disabled in a HIGH state and CPUC(0:2) clocks are synchro- nously disabled in a LOW state. 24 66IN/3V66 5 V I/O Input Connection for 66CLK(0:2) Output Clock Buffers if S2 = 1, or output DD clock for fixed 66-MHz clock if S2 = 0. See Table 1. 21, 22, 23 66B(0:2)/ V O 3.3V Clock Outputs. These clocks are buffered copies of the 66IN clock or fixed DD 3V66(2:4) at 66 MHz. See Table 1. 1, 8, 14, 19, 32, V PWR 3.3V Power Supply. DD 37, 46, 50 4, 9, 15, 20, 27, V PWR Common Ground. SS 31, 36, 47 41 V IREF PWR Current Reference Programming Input for CPU Buffers. A resistor is SS connected between this pin and IREF. This pin should also be returned to device V . SS 26 V PWR Analog Power Input. Used for phase-locked loops (PLLs) and internal analog DDA circuits. It is also specifically used to detect and determine when power is at an acceptable level to enable the device to operate.......................Document : 38-07331 Rev. *C Page 2 of 19