Si5375 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR Features Highly integrated, 4PLL clock Integrated loop filter with multiplier/jitter attenuator programmable bandwidth as low as 60 Hz Four independent DSPLLs support any-frequency synthesis Simultaneous free-run and and jitter attenuation synchronous operation Four inputs/four outputs Automatic/manual hitless input clock switching Each DSPLL can generate any frequency from 2 kHz to Selectable output clock signal 808 MHz from a 2 kHz to format (LVPECL, LVDS, CML, Ordering Information: 710 MHz input CMOS) See page 48. Ultra-low jitter clock outputs: LOL and interrupt alarm outputs 350 fs rms (12 kHz 20 MHz) 2 I C programmable and 410 fs rms (50 kHz80 MHz) Single 1.8 V 5% or 2.5 V 10% typical operation with high PSRR on- Meets ITU-T G.8251 and chip voltage regulator Telcordia GR-253-CORE OC-192 10x10 mm PBGA jitter specifications Applications High density any-port, any- 1/2/4/8/10G Fibre Channel protocol, any-frequency line GbE/10GbE Synchronous Ethernet cards Carrier Ethernet, multi-service ITU-T G.709 OTN custom FEC switches and routers 10/40/100G MSPP, ROADM, P-OTS, OC-48/192, STM-16/64 muxponders Description The Si5375 is a highly-integrated, 4-PLL, jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. Each of the DSPLL clock multiplier engines accepts an input clock ranging from 2 kHz to 710 MHz and generates an output clock ranging from 2 kHz to 808 MHz. The device provides virtually any frequency translation combination across this operating range. For asynchronous, free-running clock generation applications, the Si5375s reference oscillator can be used as a clock source for any of the four DSPLLs. The Si5375 input clock frequency and clock 2 multiplication ratio are programmable through an I C interface. The Si5375 is based on Skyworks Solutions third-generation DSPLL technology, which provides any-frequency synthesis and jitter attenuation in a highly-integrated PLL solution that eliminates the need for external VCXO and loop filter components. Each DSPLL loop bandwidth is digitally-programmable, providing jitter performance optimization at the application level. The device operates from a single 1.8 or 2.5 V supply with on-chip voltage regulators with excellent PSRR. The Si5375 is ideal for providing clock multiplication and jitter attenuation in high port count optical line cards requiring independent timing domains. Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.0 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice September 4, 2021Si5375 Functional Block Diagram PLL Bypass Input Stage Synthesis Stage Output Stage CKIN1P A N31 Input CKIN1N A Monitor PLL Bypass CKOUT1P A f f 3 OSC DSPLL NC1 NC1 HS CKOUT1N A A N32 N2 PLL Bypass CKIN1P B N31 Input CKIN1N B Monitor PLL Bypass CKOUT1P B f f 3 OSC DSPLL NC1 HS NC1 CKOUT1N B B N32 N2 PLL Bypass CKIN1P C N31 Input CKIN1N C Monitor PLL Bypass CKOUT1P C f OSC f 3 DSPLL NC1 CKOUT1N C NC1 HS C N32 N2 PLL Bypass CKIN1P D N31 Input CKIN1N D Monitor PLL Bypass CKOUT1P D f OSC f 3 DSPLL NC1 HS NC1 CKOUT1N D D N32 N2 RSTL q VDD q High PSRR Status / Control CS q Voltage Regulator GND OSC P/N Low Jitter SCL SDA LOL q IRQ q XO or Clock 2 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.0 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice September 4, 2021