Si5376 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR Features Highly-integrated, 4 PLL clock Supports all ITU G.709 and any multiplier/jitter attenuator custom FEC ratios (239/237, 255/238, 255/237, 255/236, 253/226) Four independent DSPLLs support any-frequency synthesis and jitter Integrated loop filter with attenuation programmable bandwidth 8 inputs/8 outputs Simultaneous free-run and synchronous operation Each DSPLL can generate any frequency from 2 kHz to 808 MHz Automatic/manual hitless input clock from a 2 kHz to 710 MHz input switching 350 fs rms (12 kHz 20 MHz) and Selectable output clock signal format 410 fs rms (50 kHz80 MHz) (LVPECL, LVDS, CML, CMOS) Ordering Information: typical LOL and interrupt alarm outputs Meets ITU-T G.8251 and Telcordia 2 See page 61. I C programmable GR-253-CORE OC-192 jitter Single 1.8 V 5% or 2.5 V 10% specifications operation with high PSRR on-chip Programmable loop bandwidth: voltage regulator 60 Hz to 8 kHz 10x10 mm PBGA Faster lock acquisition compared to the Si5374: <1.2 s For a very low-loop BW version, see the Si5374 Applications High-density, any-port, any-protocol, 1/2/4/8/10G Fibre Channel any-frequency line cards GbE/10 GbE Synchronous Ethernet ITU-T G.709 OTN custom FEC Carrier Ethernet, multi-service 10/40/100G switches and routers OC-48/192, STM-16/64 MSPP, ROADM, P-OTS, muxponders Description The Si5376 is a highly-integrated, 4-PLL, jitter-attenuating precision clock multiplier for applications requiring sub-1 ps jitter performance. Each of the DSPLL clock multiplier engines accepts two input clocks ranging from 2 kHz to 710 MHz and generates two independent synchronous output clocks ranging from 2 kHz to 808 MHz. The device provides virtually any frequency translation combination across this operating range. For asynchronous, free-running clock generation applications, the Si5376s reference oscillator can be used as a clock source for any of the four DSPLLs. The Si5376 input clock frequency and clock 2 multiplication ratio are programmable through an I C interface. The Si5376 is based on Skyworks Solutions third-generation DSPLL technology, which provides any-frequency synthesis and jitter attenuation in a highly-integrated PLL solution that eliminates the need for external VCXO and loop filter components. Each DSPLL loop bandwidth is digitally-programmable, providing jitter performance optimization at the application level. The device operates from a single 1.8 or 2.5 V supply with on-chip voltage regulators with excellent PSRR. The Si5376 is ideal for providing clock multiplication and jitter attenuation in high-port-count optical line cards requiring independent timing domains. Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.0 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice October 29, 2021Si5376 Functional Block Diagram PLL Bypass Input Stage Synthesis Stage Output Stage CKIN1P A PLL Bypass CKOUT1P A N31 Input CKIN1N A Monitor CKOUT1N A NC1 f3 f DSPLL OSC NC1 HS CKIN2P A Hitless A Switch CKIN2N A NC2 N32 CKOUT2P A Internal Osc PLL Bypass CKOUT2N A N2 PLL Bypass CKIN3P B PLL Bypass CKOUT3P B N31 Input CKIN3N B Monitor NC1 CKOUT3N B f3 DSPLL f OSC NC1 HS CKIN4P B Hitless B Switch CKIN4N B NC2 N32 CKOUT4P B Internal Osc PLL Bypass CKOUT4N B N2 PLL Bypass CKIN5P C PLL Bypass N31 CKOUT5P C Input CKIN5N C Monitor CKOUT5N C NC1 f 3 f DSPLL OSC NC1 HS CKIN6P C Hitless C Switch CKIN6N C NC2 N32 CKOUT6P C Internal Osc PLL Bypass CKOUT6N C N2 PLL Bypass CKIN7P D PLL Bypass CKOUT7P D N31 Input CKIN7N D Monitor CKOUT7N D NC1 f 3 f DSPLL OSC NC1 HS CKIN8P D Hitless D Switch CKIN8N D NC2 N32 CKOUT8P D Internal Osc PLL Bypass CKOUT8N D N2 RSTL q VDD q High PSRR Status / Control CS CA q Voltage Regulator GND OSC P/N Low Jitter SCL SDA LOL q IRQ q XO or Clock 2 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.0 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice October 29, 2021