Si5386 Data Sheet 12-Channel, Any-Frequency, Any-Output wireless Jitter Attenu- KEY FEATURES ator / Clock Multiplier with Ultra-Low Noise Flexible timing in a single IC The Si5386 is an ultra high performance wireless jitter attenuator with any frequency Generates any combination of output outputs for eCPRI (ethernet-based Common Public Radio Interface) applications, frequencies from any input frequency which demand the highest level of integration and phase noise performance. Based Input frequency range: on Silicon Laboratories 4th generation DSPLL technology, the Si5386 combines Differential: 7.68 MHz to 750 MHz frequency synthesis and jitter attenuation in a highly integrated digital solution with a LVCMOS: 7.68 MHz to 250 MHz cost-effective oscillator, and without the need of any external loop filter components. The fixed frequency oscillator provides frequency stability for free-run and holdover Output frequency range (Integer): modes. This all-digital solution provides superior performance that is highly immune Differential: up to 2.94912 GHz to external board disturbances such as power supply noise. Output frequency range (fractional): Differential: up to 735 MHz eCPRI-based remote radio heads and fixed wireless systems require a diverse set LVCMOS: up to 250 MHz of clocks such as ADC/DAC, RF LOs, and Ethernet clocks. The Si5386 architecture Ultra-low RMS jitter: is designed to deliver high-performance JESD204B DCLK and SYSREF clock pairs 72 fs typ (12 kHz20 MHz) and flexible any-rate clocks for non-CPRI clocks such as Ethernet and system refer- ence clocks all from a single IC. Phase noise of 122.88MHz carrier frequency: 118 dBc/Hz 100Hz offset ITU-T G.8262 compliant Applications: Wireless Infrastructure eCPRI RRH (Remote Radio Head) BBU (Baseband Unit) Small Cell and BTS DOCSIS Test and Measurement 54 MHz OSC IN SEL INT IN0 DSPLL INT IN1 INT OUT0A INT IN2 INT OUT0 IN3/FB IN INT INT 0 OUT1 Multi INT OUT2 Synth INT OUT3 Multi Synth INT OUT4 Multi Synth INT 0 OUT5 Multi I2C SEL Synth INT OUT6 SDA/SDIO SPI/ Multi A1/SDO 2 INT OUT7 I C Synth SCLK A0/CS INT OUT8 NVM INT OUT9 0 LOL Status Monitors INTR INT OUT9A PDN RST SYNC OE Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com 1 Rev. 1.02 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice July 26, 2021 1Table of Contents 1. Features List ...............................4 2. Ordering Guide ..............................5 3. Functional Description............................6 3.1 Frequency Configuration ..........................6 3.2 DSPLL Loop Bandwidth...........................6 3.3 Fastlock Feature .............................6 3.4 Modes of Operation ............................6 3.4.1 Initialization and Reset..........................7 3.4.2 Freerun Mode.............................7 3.4.3 Lock Acquisition Mode..........................7 3.4.4 Locked Mode.............................7 3.4.5 Holdover Mode ............................8 3.4.6 VCO Freeze Mode ...........................8 3.5 External Reference (XA/XB) .........................9 3.6 Inputs (IN0, IN1, IN2, IN3) ..........................9 3.6.1 Manual Input Switching (IN0, IN1, IN2, IN3)...................9 3.6.2 Automatic Input Selection (IN0, IN1, IN2, IN3)..................10 3.6.3 Hitless Input Switching..........................10 3.6.4 Ramped Input Switching .........................10 3.6.5 Glitchless Input Switching.........................10 3.7 Fault Monitoring .............................10 3.7.1 Input LOS Detection...........................11 3.7.2 Reference Clock LOS Detection.......................11 3.7.3 OOF Detection ............................11 3.7.4 LOL Detection.............................12 3.7.5 Interrupt Pin (INTRb) ..........................13 3.8 Outputs ................................13 3.8.1 Output Crosspoint ...........................14 3.8.2 Output Signal Format ..........................14 3.8.3 Output Terminations...........................15 3.8.4 Programmable Amplitude For Differential Outputs.................15 3.8.5 LVCMOS Output Impedance and Drive Strength Selection..............16 3.8.6 LVCMOS Output Signal Swing .......................16 3.8.7 LVCMOS Output Polarity.........................16 3.8.8 Output Enable/Disable..........................16 3.8.9 Output Disable During LOL ........................16 3.8.10 Output Disable During Reference LOS....................16 3.8.11 Output Driver State When Disabled .....................16 3.8.12 Synchronous Output Disable Feature ....................17 3.8.13 Static Output Skew Control........................17 3.8.14 Dynamic Output Skew Control.......................17 3.8.15 Zero Delay Mode ...........................17 3.8.16 Output Divider (R) Synchronization .....................18 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com 2 Rev. 1.02 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice July 26, 2021 2