3.3 mm3.3 mm SiZF5302DT www.vishay.com Vishay Siliconix Dual N-Channel 30 V (D-S) MOSFET FEATURES PowerPAIR 3 x 3FS TrenchFET Gen V power MOSFET V+ V+ 4 LSG Symmetric dual N-channel 3 5 GND 2 Flip chip technology optimal thermal design 1 6 V+ High side and low side MOSFETs form optimized GND combination for 50 % duty cycle 12 7 Optimized R - Q and R - Q FOM elevates efficiency DS g DS gd 8 HSG 11 for high frequency switching 9 SW 10 SW 100 % R and UIS tested 11 g SW Material categorization: for definitions of compliance Top View Bottom View please see www.vishay.com/doc 99912 V+ APPLICATIONS PRODUCT SUMMARY Synchronous buck V (V) 30 DS Computer / server peripherals R max. () at V = 10 V 0.0032 DS(on) GS HSG max. () at V = 4.5 V 0.0053 R DS(on) GS Half bridge N-Channel 1 Q typ. (nC) 6.7 SW g MOSFET POL a I (A) 100 D Telecom DC/DC Configuration Dual LSG N-Channel 2 GND MOSFET ORDERING INFORMATION Package PowerPAIR 3 x 3FS Lead (Pb)-free and halogen-free SiZF5302DT-T1-RE3 ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A PARAMETER SYMBOL LIMIT UNIT Drain-source voltage V 30 DS V Gate-source voltage V +16 / -12 GS T = 25 C 100 C T = 70 C 80 C Continuous drain current (T = 150 C) I J D b, c T = 25 C 28.1 A b, c T = 70 C 22.5 A A Pulsed drain current (t = 100 s) I 150 DM T = 25 C 40.1 C Continuous source current (MOSFET diode conduction) I S b, c T = 25 C 3.2 A Single pulse avalanche current I 17 AS L = 0.1 mH Single pulse avalanche energy E 14.45 mJ AS T = 25 C 48.1 C T = 70 C 30.8 C Maximum power dissipation P W D b, c T = 25 C 3.8 A b, c T = 70 C 2.4 A Operating junction and storage temperature range T , T -55 to +150 J stg C Soldering recommendations (peak temperature) 260 Notes a. T = 25 C C b. Surface mounted on 1 x 1 FR4 board c. t = 10 s S22-0207-Rev. A, 28-Feb-2022 Document Number: 62055 1 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 3.3 mm3.3 mmSiZF5302DT www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYPICAL MAXIMUM UNIT a, b Maximum junction-to-ambient t 10 s R 26 33 thJA C/W Maximum junction-to-case (drain) Steady state R 22.6 thJC Notes a. Surface mounted on 1 x 1 FR4 board b. Maximum under steady state conditions is 67 C/W SPECIFICATIONS (T = 25 C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-source breakdown voltage V V = 0 V, I = 1 mA 30 - - DS GS D V Gate-source threshold voltage V V = V , I = 250 A 1 - 2 GS(th) DS GS D Gate-source leakage I V = 0 V, V = +16 V / -12 V - - 100 nA GSS DS GS V = 24 V, V = 0 V - - 1 DS GS Zero gate voltage drain current I A DSS V = 24 V, V = 0 V, T = 55 C - - 5 DS GS J a On-state drain current I V 5 V, V = 10 V 30 - - A D(on) DS GS V = 10 V, I = 10 A - 0.0027 0.0032 GS D a Drain-source on-state resistance R DS(on) V = 4.5 V, I = 7 A - 0.0044 0.0053 GS D a Forward transconductance g V = 10 V, I = 10 A - 57 - S fs DS D b Dynamic Input capacitance C - 1030 - iss Output capacitance C - 340 - pF oss V = 15 V, V = 0 V, f = 1 MHz DS GS Reverse transfer capacitance C -30 - rss C /C ratio - 0.028 0.055 rss iss V = 15 V, V = 10 V, I = 20 A - 14.8 22.2 DS GS D Total gate charge Q g - 6.7 10.0 nC Gate-source charge Q V = 15 V, V = 4.5 V, I = 20 A -3.8 - gs DS GS D Gate-drain charge Q -1.12 - gd Gate resistance R f = 1 MHz 0.24 1.2 2.4 g Turn-on delay time t -10 20 d(on) Rise time t -6 12 r V = 15 V, R = 1 , I 15 A, DD L D V = 10 V, R = 1 GEN g Turn-off delay time t -23 46 d(off) Fall time t -6 12 f ns Turn-on delay time t -20 40 d(on) Rise time t -45 90 r V = 15 V, R = 1 , I 15 A, DD L D V = 4.5 V, R = 1 GEN g Turn-off delay time t -20 40 d(off) Fall time t -12 24 f Drain-source Body Diode Characteristics Continuous source-drain diode current I T = 25C - - 40.1 S C A Pulse diode forward current I - - 150 SM Body diode voltage V I = 15 A, V = 0 V - 0.85 1.2 V SD S GS Body diode reverse recovery time t -13 26 ns rr Body diode reverse recovery charge Q -3 6 nC rr I = 15 A, di/dt = 100 A/s, F T = 25 C J Reverse recovery fall time t -6 - a ns Reverse recovery rise time t -7 - b Notes a. Pulse test pulse width 300 s, duty cycle 2 % b. Guaranteed by design, not subject to production testing Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S22-0207-Rev. A, 28-Feb-2022 Document Number: 62055 2 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000