Dual DPLL Digitized Clock Synchronizer Data Sheet AD9546 FEATURES APPLICATIONS Digitized clock transport subsystem 5G timing transport high precision synchronization 9 independent UTS blocks (time stamp egress ports) Global positioning system (GPS), precision time protocol 2 independent IUTS blocks (time stamp ingress ports) (PTP) (IEEE 1588), and synchronous Ethernet (SyncE) jitter Dual DPLL synchronizes 1 Hz to 750 MHz physical layer cleanup and synchronization clocks, providing frequency translation with jitter Optical transport networks (OTN), synchronous digital cleaning of noisy references hierarchy (SDH), and macro and small cell base stations Complies with ITU-T G.8262 and Telcordia GR-253 Small base station clocking (baseband and radio) Supports Telcordia GR-1244, ITU-T G.812, ITU-T G.813, Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2 cleanup, and phase transient control Continuous frequency monitoring and reference validation JESD204B support for analog-to-digital converter (ADC) and 8 for frequency deviation as low as 50 ppb (5 10 ) digital-to-analog converter (DAC) clocking Both DPLLs feature a 24-bit fractional divider with 24-bit Carrier Ethernet programmable modulus GENERAL DESCRIPTION Programmable digital loop filter bandwidth: 0.0001 Hz to The AD9546 incorporates digitized clocking technology that 1850 Hz efficiently transports and distributes clock signals in systems. 2 independent, programmable auxiliary NCOs (1 Hz to Digitized clocking allows the design of flexible and scalable 65,535 Hz, resolution < 1.37 pHz), suitable for IEEE 1588 clock transport systems with well controlled phase (time) Version 2 servo feedback in PTP applications alignment. These characteristics make the AD9546 a leading Automatic and manual holdover and reference switchover, choice for the design of network equipment that must meet the providing zero delay, hitless, or phase buildout operation synchronization requirements for IEEE 1588 boundary clocks Programmable priority-based reference switching with per ITU-T G.8273.2 Class D. Digitized clocking is also relevant manual, automatic revertive, and automatic nonrevertive in applications requiring the accurate transport of frequency modes supported and phase to multiple usage endpoints (for example, 5 pairs of clock output pins with each pair useable as distributing synchronized system reference (SYSREF) clocks to differential LVDS/HCSL/CML or as 2 single-ended outputs an array of ADC channels). (1 Hz to 500 MHz) 2 differential or 8 single-ended input references The AD9546 supports existing and emerging International Crosspoint mux interconnects reference inputs to PLLs Telecommunications Union (ITU) standards for the delivery of Supports embedded (modulated) input/output clock signals frequency, phase, and time of day over service provider packet Fast DPLL locking modes networks (ITU-T G.8262, ITU-T G.812, ITU-T G.813, ITU-T Provides internal capability to combine the low phase noise G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2). of a crystal resonator or crystal oscillator with the The 10 clock outputs of the AD9546 synchronize to any one of frequency stability and accuracy of a TCXO or OCXO up to eight input references. The digital phase-locked loops External EEPROM support for autonomous initialization (DPLLs) reduce timing jitter associated with the external Single 1.8 V power supply operation with internal regulation references, and the analog phase-locked loops (APLLs) provide Built in temperature monitor and alarm and temperature frequency translation with low jitter output clocks. The digitally compensation for enhanced zero delay performance controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail. The AD9546 is available in a 48-lead LFCSP (7 mm 7 mm) package and operates over the 40C to +85C temperature range. Throughout this data sheet, a single function of a multifunction pin name may be referenced when only that function is relevant (for example, M5 for SDO/M5). Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 2020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. AD9546 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Logic Output Specifications (M0 to CSB/M6 Pins) .............. 31 Applications ...................................................................................... 1 Serial Port Specifications ........................................................... 32 General Description ......................................................................... 1 Jitter Generation (Random Jitter) ............................................ 34 Revision History ............................................................................... 5 Phase Noise ................................................................................. 35 Functional Block Diagram .............................................................. 6 Absolute Maximum Ratings ......................................................... 38 Specifications .................................................................................... 7 Thermal Resistance .................................................................... 38 Operating Temperature ............................................................... 7 ESD Caution ............................................................................... 38 Supply Voltage .............................................................................. 7 Pin Configuration and Function Descriptions .......................... 39 Supply Current ............................................................................. 7 Typical Performance Characteristics .......................................... 42 Power Dissipation ........................................................................ 8 Terminology .................................................................................... 47 System Clock Inputs, XOA and XOB ........................................ 9 Theory of Operation ...................................................................... 48 Reference Inputs ......................................................................... 10 Input/Output Termination Recommendations ......................... 49 Reference to Reference Coupling ............................................. 12 System Clock Inputs .................................................................. 49 REFx to REFx Input Timing Skew ........................................... 14 Reference Clock Inputs ............................................................. 49 REFx to Auxiliary REFx Input Timing Skew ......................... 15 Clock Outputs ............................................................................. 50 Reference Monitors .................................................................... 16 Digitized Clocking.......................................................................... 52 Distribution Clock Outputs ...................................................... 17 Overview ...................................................................................... 52 Output to Output Timing Skew ............................................... 19 System Clock PLL Component ................................................ 52 Output Timing Skew Between Mx Pins and OUTxyP and/or Common Clock DPLL Component ........................................ 52 OUTxyN Pins ............................................................................. 20 Physical Clock Converter .......................................................... 52 Time Duration of Digital Functions ........................................ 20 Physical Clock Generator .......................................................... 52 DPLL0 and DPLL1 Specifications ............................................ 21 Common Clock Synchronizer Component ........................... 54 DPLL Lock Detection Specifications ....................................... 21 User Time Stamper (UTS) and Inverse User Timer Stamper DPLL Phase Characteristics ...................................................... 22 (IUTS) Components .................................................................. 54 DPLL Propagation Delay .......................................................... 23 A Digitized Clocking Node Example ...................................... 54 DPLL Propagation Delay Variation ........................................ 24 Common Clock DPLL (CCDPLL) ............................................... 56 Holdover Specifications............................................................. 25 Overview ...................................................................................... 56 Analog PLL (APLL0 and APLL1) Specifications ................... 25 Common Clock References ...................................................... 56 Output Channel Divider Specifications .................................. 25 Common Clock Reference Monitor ........................................ 57 Time to Digital Converter (TDC) Specifications .................. 26 CCDPLL Lock Detector ............................................................ 57 Auxiliary NCO Specifications .................................................. 26 CCDPLL Loop Filter .................................................................. 57 Common Clock DPLL Specifications ...................................... 26 Common Clock Reference (CCR) Period Declaration ......... 57 Common Clock Synchronizer (CCS) Specifications ............ 27 Common Clock Reference Switchover ................................... 58 User Time Stampers (UTS) Specifications ............................. 27 Active Status ................................................................................ 58 Inverse User Time Stampers (IUTS) Specifications .............. 28 Common Clock Synchronizer (CCS) .......................................... 59 Analog Loopback (Round Trip Delay) Specifications .......... 29 Overview ...................................................................................... 59 Mx to Mx Pin Output Timing Skew ........................................ 30 Synchronization Source ............................................................ 60 System Clock Compensation Specifications .......................... 30 Tagged Synchronization ........................................................... 60 Temperature Sensor Specifications ......................................... 30 Synchronization Time ............................................................... 61 Logic Input Specifications (RESETB, M0 to CSB/M6 Pins) 30 Adding Time Skew to the Synchronization Time ................. 62 Rev. 0 Page 2 of 205