Femtoclock Crystal-to-3.3V LVPECL 843002 Data Sheet Frequency Synthesizer GENERAL DESCRIPTION FEATURES Two 3.3V LVPECL outputs The 843002 is a two output LVPECL synthesizer optimized to generate Fibre Channel reference clock frequencies . Using Selectable crystal oscillator interface a 26.5625MHz, 18pF parallel resonant crystal, the following or LVCMOS/LVTTL single-ended input frequencies can be generated based on the 2 frequency select pins Supports the following output frequencies: 212.5MHz, (F SEL 1:0 ): 212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz, rd 187.5MHz, 159.375MHz, 106.25MHz and 53.125MHz and 53.125MHz. The 843002 uses IDTs 3 generation low phase noise VCO technology and can achieve 1ps or lower typical rms VCO range: 560MHz - 680MHz phase jitter, easily meeting Fibre Channel jitter requirements. The 843002 is packaged in a small 20-pin TSSOP package. RMS phase jitter (637kHz - 10MHz): 0.72ps (typical) Typical phase noise at 212.5MHz Phase noise: Offset Noise Power 100Hz ................-87.7 dBc/Hz 1KHz ..............-111.6 dBc/Hz 10KHz ..............-124.3 dBc/Hz 100KHz ..............-124.3 dBc/Hz Full 3.3V supply mode Lead-Free package RoHS compliant -30C to 85C ambient operating temperature FREQUENCY SELECT FUNCTION TABLE PIN ASSIGNMENT Inputs Output Input Fre- Frequency M Divider N Divider M/N quency F SEL1 F SEL0 (MHz) Value Value Divider Value (MHz) 26.5625 0 0 24 3 8 212.5 26.5625 0 1 24 4 6 159.375 26.5625 1 0 24 6 4 106.25 26.5625 1 1 24 12 2 53.125 23.4375 0 0 24 3 8 187.5 843002 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm BLOCK DIAGRAM package body G Package Pulldown 2 F SEL 1:0 Top View Pulldown nPLL SEL Q0 F SEL 1:0 nQ0 0 0 3 Pulldown TEST CLK 11 0 1 4 1 1 0 6 26.5625MHz 1 1 12 Q1 XTAL IN VCO Phase 0 OSC 637.5MHz 0 Detector nQ1 (w/26.5625MHz XTAL OUT Reference) Pulldown nXTAL SEL M = 24 (fixed) Pulldown MR 2016 Integrated Device Technology, Inc 1 Revision B January 21, 2016843002 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 7 nc Unused No connect. 2, 20 V Power Output supply pins. CCO 3, 4 Q0, nQ0 Ouput Differential output pair. LVPECL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx 5 MR Input Pulldown to go high. When logic LOW, the internal dividers and the outputs are en- abled. LVCMOS/LVTTL interface levels. Selects between the PLL and TEST CLK as input to the dividers. When 6 nPLL SEL Input Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. 8V Power Analog supply pin. CCA F SEL0, 9, 11 Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. F SEL1 10, 16 V Power Core supply pin. CC XTAL OUT, Parallel resonant crystal interface. XTAL OUT is the output, 12, 13 Input XTAL IN XTAL IN is the input. 14 TEST CLK Input Pulldown LVCMOS/LVTTL clock input. Selects between crystal or TEST CLK inputs as the the PLL Reference 15 nXTAL SEL Input Pulldown source. Selects XTAL inputs when LOW. Selects TEST CLK when HIGH. LVCMOS/LVTTL interface levels. 17 V Power Negative supply pins. EE 18, 19 nQ1, Q1 Output Differential output pair. LVPECL interface levels. NOTE: Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pulldown Resistor 51 k PULLDOWN 2016 Integrated Device Technology, Inc 2 Revision B January 21, 2016