CLK SEL FemtoClock NG Crystal-to-3.3V LVPECL ICS843N3960I Clock Generator DATA SHEET General Description Features The ICS843N3960I is a LVPECL Clock Synthesizer. The Fourth Generation FemtoClock NG PLL technology ICS843N3960I can synthesize 100MHz, 125MHz, 156.25MHz and Two differential LVPECL outputs 212.5MHz from a single 25MHz crystal or reference clock. Crystal oscillator interface designed for 12pF, 25MHz parallel Utilizing an external loop filter capacitor, the ICS843N3960I is resonant crystal capable of holdover mode when the main reference clock becomes CLK/nCLK input pair can accept the following differential input unstable, making this ideal for redundant timing applications. levels: LVPECL, LVDS, HCSL RMS phase jitter at 100MHz (12kHz 20MHz): 0.510ps (max.) RMS phase jitter at 125MHz (12kHz 20MHz): 0.575ps (max.) RMS phase jitter at 156.25MHz (12kHz 20MHz): 0.504ps (max.) RMS phase jitter at 212.5MHz (12kHz 20MHz): 0.512ps (max.) 3.3V power supply -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignment Block Diagram FSEL 0 1 20 V Pullup CC OE FSEL 1 2 19 V CCA LOR V OE 3 18 CC Pulldown CLK SEL Q1 4 17 Q0 nQ1 5 16 nQ0 XTAL IN V 6 15 LOR EE Xtal 25 MHz Osc. V CP 7 14 EE XTAL OUT V EE 8 13 0 Q0 nCLK XTAL IN 9 12 Phase LOR nQ0 Pullup Detector CLK XTAL OUT CLK 10 11 FemtoClock NG 25MHz 1 + /N VCO nCLK Charge Q1 Pullup / Pump ICS843N3960I Pulldown nQ1 20 Lead TSSOP, E-Pad 6.5mm x 4.4mm x 0.925mm /M package body G Package Pulldown FSEL 0 Divider Top View Control Pulldown FSEL 1 Logic ICS843N3960DGI REVISION B SEPTEMBER 24, 2012 1 2012 Integrated Device Technology, Inc. CPICS843N3960I Data Sheet FEMTOCLOCK NG CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR Table 1. Pin Descriptions Number Name Type Description FSEL0, 1, 2 Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. See Table 3A. FSEL1 3 OE Input Pullup Active HIGH output enable. LVCMOS/LVTTL interface levels. 4, 5 Q1, nQ1 Output Differential output pair. 3.3V LVPECL interface levels. 6, 8, 14 V Power Negative supply pins. EE 7 CP Output External loop filter capacitor output pin. Pullup/ 9 nCLK Input Inverting differential clock input. Internal resistor bias to V /2. CC Pulldown 10 CLK Input Pulldown Non-inverting differential clock input. XTAL OUT 11, 12 Input Crystal oscillator interface. XTAL IN is the input, XTAL OUT is the output. XTAL IN 13 CLK SEL Input Pulldown Input source control pin. LVCMOS/LVTTL interface levels. See Table 3C. 15 LOR Output Loss of Reference output pin. See LOR Functionality section. 16, 17 nQ0, Q0 Output Differential output pair. 3.3V LVPECL interface levels. 18, 20 V Power Core supply pins. CC 19 V Power Analog supply pin. CCA NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 3.5 pF IN Input Pulldown Resistor 51 k R PULLDOWN R Input Pullup Resistor 51 k PULLUP R Output Impedance LOR 18 OUT ICS843N3960DGI REVISION B SEPTEMBER 24, 2012 2 2012 Integrated Device Technology, Inc.