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9LPRS502SFLF

9LPRS502SFLF electronic component of Renesas

Datasheet
Clock Synthesizer / Jitter Cleaner PC MAIN CLOCK

Manufacturer: Renesas
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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MOQ : 1
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9LPRS502SFLF
Renesas

1 : USD 17.7
10 : USD 16.45
26 : USD 15.144
104 : USD 13.548
260 : USD 13.032
520 : USD 12.396
1014 : USD 11.616
2522 : USD 11.616
5018 : USD 11.604
N/A

Obsolete
     
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Datasheet ICS9LPRS502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Recommended Application: Key Specifications: CPU outputs cycle-cycle jitter < 85ps CK505 compliant clock with fully integrated voltage regulator and Internal series resistor on differential outputs, SRC output cycle-cycle jitter < 125ps PCIe Gen 1 compliant PCI outputs cycle-cycle jitter < 250ps +/- 100ppm frequency accuracy on CPU & SRC Output Features: clocks 2 - CPU differential low power push-pull pairs 7 - SRC differential low power push-pull pairs Features/Benefits: 1 - CPU/SRC selectable differential low power push-pull Does not require external pass transistor for voltage pair regulator 1 - SRC/DOT selectable differential low power push-pull Integrated series resistors on differential outputs, pair Z =50W o 5 - PCI, 33MHz Supports spread spectrum modulation, default is 0.5% 1 - PCI F, 33MHz free running down spread 1 - USB, 48MHz Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning 1 - REF, 14.318MHz One differential push-pull pair selectable between SRC and two single-ended outputs Table 1: CPU Frequency Select Table Pin Configuration 2 1 1 PCICLK0/CR A 1 56 SCLK CPU SRC PCI REF USB DOT FSLC FSLB FSLA VDDPCI 2 55 SDATA MHz MHz MHz MHz MHz MHz B0b7 B0b6 B0b5 PCICLK1/CR B 3 54 FSLC/TEST SEL/REF0 0 0 0 266.66 PCICLK2/LTE 4 53 VDDREF 0 0 1 133.33 PCICLK3 5 52 X1 0 1 0 200.00 PCICLK4/SRC5 EN 6 51 X2 100.00 33.33 14.318 48.00 96.00 0 1 1 166.66 PCI F5/ITP EN 7 50 GNDREF 1 0 0 333.33 GNDPCI 8 49 FSLB/TEST MODE VDD48 9 48 CK PWRGD/PD 1 0 1 100.00 USB 48MHz/FSLA 10 47 VDDCPU 1 1 0 400.00 GND48 11 46 CPUCLKT0 11 1 Reserved VDD96I/O 12 45 CPUCLKC0 1. FS A and FS B are low-threshold inputs.Please see V and V specifications in L L IL FS IH FS DOTT 96/SRCCLKT0 13 44 GNDCPU the Input/Supply/Common Output Parameters Table for correct values. DOTC 96/SRCCLKC0 14 43 CPUCLKT1 Also refer to the Test Clarification Table. GND 15 42 CPUCLKC1 2. FS C is a three-level input. Please see the V and V L IL FS IH FS VDD 16 41 VDDCPUI/O specifications in the Input/Supply/Common Output Parameters Table for correct values. SRCCLKT1/SE1 17 40 NC SRCCLKC1/SE2 18 39 CPUCLKT2 ITP/SRCCLKT8 GND 19 38 CPUCLKC2 ITP/SRCCLKC8 VDDPLL3I/O 20 37 VDDSRCI/O SRCCLKT2/SATACLKT 21 36 SRCCLKT7/CR F SRCCLKC2/SATACLKC 22 35 SRCCLKC7/CR E GNDSRC 23 34 GNDSRC SRCCLKT3/CR C 24 33 SRCCLKT6 SRCCLKC3/CR D 25 32 SRCCLKC6 VDDSRCI/O 26 31 VDDSRC SRCCLKT4 27 30 PCI STOP /SRCCLKT5 SRCCLKC4 28 29 CPU STOP /SRCCLKC5 56-SSOP/TSSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor TM TM IDT /ICS 56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1125E02/26/09 1 ICS 9LPRS502 ICS9LPRS502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information SSOP/TSSOP Pin Description PIN PIN NAME TYPE DESCRIPTION 3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR A EN bit located in byte 5 of SMBUs address space. 1 PCI0/CR A I/O Byte 5, bit 7 0 = PCI0 enabled (default) 1= CR A enabled. Byte 5, bit 6 controls whether CR A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR A controls SRC0 pair (default), 1= CR A controls SRC2 pair 2 VDDPCI PWR Power supply pin for the PCI outputs, 3.3V nominal 3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR B EN bit located in byte 5 of SMBUs address space. 3 PCI1/CR B I/O Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR B enabled. Byte 5, bit 6 controls whether CR B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR B controls SRC1 pair (default) 1= CR B controls SRC4 pair 3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on power- up as follows 4PCI2/TME I/O 0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed After being sampled on power-up, this pin becomes a 3.3V PCI Output 5 PCI3 OUT 3.3V PCI clock output. 3.3V PCI clock output / SRC5 pair or PCI STOP /CPU STOP enable strap. On powerup, the logic value on this pin determines if the SRC5 pair is enabled or if CPU STOP /PCI STOP is 6 PCI4/SRC5 EN I/O enabled (pins 29 and 30). The latched value controls the pin function on pins 29 and 30 as follows 0 = PCI STOP /CPU STOP 1 = SRC5/SRC5 Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI STOP pin. On powerup, the state of this pin determines whether pins 38 and 39 are an 7 PCI F5/ITP EN I/O ITP or SRC pair. 0 =SRC8/SRC8 1 = ITP/ITP 8 GNDPCI PWR Ground for PCI clocks. 9 VDD48 PWR Power supply for USB clock, nominal 3.3V. Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to 10 USB 48MHz/FSLA I/O input electrical characteristics for Vil FS and Vih FS values. 11 GND48 PWR Ground pin for the 48MHz outputs. 12 VDD96 IO PWR Power supply for DOT96 output. 1.05 to 3.3V +/-5%. True clock of SRC or DOT96. The power-up default function is SRC0. After powerup, this pin function may be changed to DOT96 via SMBus Byte 1, bit 7 as follows: 13 DOTT 96/SRCT0 OUT 0= SRC0 1=DOT96 Complement clock of SRC or DOT96. The power-up default function is SRC0 . After powerup, this pin function may be changed to DOT96 via SMBus Byte 1, bit 7 as follows 14 DOTC 96/SRCC0 OUT 0= SRC0 1=DOT96 15 GND PWR Ground pin for the DOT96 clocks. 16 VDD PWR Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal. TM TM IDT /ICS 56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1125E02/26/09 2

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8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
CEL (RENESAS)
ID4
IDT
IDT, Integrated Device Technology Inc
INTEGRATED DEVICE
INTEGRATED DEVICE TECHNOLOGY
INTEGRATED DEVICES TECH AID
Intersil
INTERSIL - FGC
Intersil(Renes as Electronics)
Intersil(Renesas Electronics)
ITS
REA
RENESAS
RENESAS (IDT)
RENESAS (INTERSIL)
Renesas / IDT
Renesas / Intersil
Renesas Electronics
Renesas Electronics America
RENESAS TECHNOLOGY

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