800MHz Low Voltage PECL Clock Synthesizer MPC9230 DATA SHEET The MPC9230 is a 3.3 V compatible, PLL based clock synthesizer targeted for high perfor- mance clock generation in mid-range to high-performance telecom, networking and computing (1) MPC9230 applications. With output frequencies from 50 MHz to 800 MHz and the support of differential PECL output signals the device meets the needs of the most demanding clock applications. Features 800 MHz LOW VOLTAGE (1) 50 MHz to 800 MHz synthesized clock output signal CLOCK SYNTHESIZER Differential PECL output LVCMOS compatible control inputs On-chip crystal oscillator for reference frequency generation Alternative LVCMOS compatible reference clock input FN SUFFIX 3.3 V power supply 28-LEAD PLCC PACKAGE Fully integrated PLL CASE 776-02 Minimal frequency overshoot Serial 3-wire programming interface Parallel programming interface for power-up EI SUFFIX 28-LEAD PLCC PACKAGE 32-lead LQFP and 28-lead PLCC packaging Pb-FREE PACKAGE 32-lead and 28-lead Pb-free package available CASE 776-02 SiGe Technology Ambient temperature range -40C to +85C FA SUFFIX Pin and function compatible to the MC12430 32-LEAD LQFP PACKAGE CASE 873A-04 AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-04 Functional Description The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal (1) oscillator is divided by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1600 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency f , the PLL feedback-divider XTAL M and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M/4 times the external input reference frequency. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is (1) within the specified VCO frequency range (800 to 1600 MHz ). The M-value must be programmed by the serial or parallel interface. The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 to V 2.0 V. The positive supply voltage for the internal PLL CC is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M 8:0 and N 1:0 inputs to configure the internal counters. It is recommended on system reset to hold the P LOAD input LOW until power becomes valid. On the LOW-to-HIGH transition of P LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M 8:0 and N 1:0 inputs and prevent the LVCMOS compatible control inputs from floating. The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S CLOCK input. The serial input S DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S LOAD input. See the programming section for more information. The TEST output reflects various internal node values, and is controlled by the T 2:0 bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output. 1.The VCO frequency range of 8001600 MHz is available at an ambient temperature range of 0 to 70C. At 40 to +85C, the VCO frequency (output frequency) is limited to max. 1500 MHz (750 MHz). MPC9230 REVISION 8 MARCH 29, 2010 1 2010 Integrated Device Technology, Inc.MPC9230 Data Sheet 800MHZ LOW VOLTAGE PECL CLOCK SYNTHESIZER XTAL IN XTAL VCO 1 11 XTAL OUT Ref 1 2 10 20 M 00 FOUT PLL OE 4 01 F OUT 800 1600 M FREF EXT 8 10 FB V CC 0 TO 5 Test Test 9-BIT M-Divider XTAL SEL 3 2 9 V CC M-Latch N-Latch T-Latch LE P LOAD S LOAD P/S 01 0 1 Bits 3-4 Bits 5-13 Bits 0-2 S DATA 14-Bit Shift Register S CLOCK V CC M 0:8 N 1:0 OE Figure 1. MPC9230 Logic Diagram 24 23 22 21 20 19 18 17 25 24 23 22 21 20 19 S CLOCK 25 16 NC GND 26 18 N 1 26 15 M 3 TEST S DATA N 0 27 17 V 27 14 M 2 CC M 8 S LOAD 16 28 V 28 13 M 1 CC M 7 V 1 MPC9230 MPC9230 15 CC PLL 29 12 GND M 0 FREF EXT M 6 14 2 F 30 11 P LOAD OUT XTAL SEL M 5 3 13 31 10 FOUT OE XTAL IN M 4 32 9 4 12 V XTAL OUT CC 12 34 56 78 5 6 78 9 10 11 Figure 2. MPC9230 28-Lead PLCC Pinout Figure 3. MPC9230 32-Lead Package Pinout (Top View) (Top View) MPC9230 REVISION 8 MARCH 29, 2010 2 2010 Integrated Device Technology, Inc. XTAL OUT V CC OE FOUT F P LOAD OUT M 0 GND M 1 V CC M 2 TEST M 3 GND S CLOCK NC N 1 S DATA S LOAD N 0 M 8 V CC PLL M 7 V CC PLL M 6 FREF EXT M 5 XTAL SEL M 4 XTAL IN