RC22504A000GNK#BB0 Renesas

Datasheet RC22504A FemtoClock 2 Sub-100fs Frequency Synthesizer The RC22504A is a small, low-power timing Can configure itself automatically after reset via component designed to be placed immediately internal customer-definable One-Time adjacent to a PHY, switch, ASIC or FPGA that Programmable (OTP) memory with up to four requires several reference clocks with jitter different configurations performance less than 100fs (max). The RC22504A 4 4 mm 24-QFN package can act as a frequency synthesizer to locally generate the reference clock or as a DCO for frequency Block Diagram margining or OTN clock applications. Lock Detect LOCK The device is a member of Renesas high- performance FemtoClock2 family. Out OUT0 Div XTAL/ FracN Osc XO Applications APLL Out Reference clock generator for 100Gbps / 400Gbps OUT1 Div PHYs or switches CLKIN Adjustable OTN clock reference for OTU3 / OTU4 Out OUT2 Div mappers 2 I C / SPI Registers OTP Reference clock for programmable FiberOptic Out OUT3 Modules Div SEL OE Features Jitter as low as 64 fs RMS maximum (10Hz to 20MHz) PLL core consists of fractional-feedback Analog PLL (APLL) Operates from a 25MHz to 80MHz crystal or XO APLL frequency independent of input / crystal frequency Operates as a frequency synthesizer or Digitally Controlled Oscillator (DCO) DCO has tuning granularity of < 1ppb Programmable status output 4 differential / 8 LVCMOS outputs Any frequency from 10MHz to 1GHz (180MHz for LVCMOS) Programmable output buffer supports HCSL (DC-coupled), LVDS/LVPECL/CML (AC-coupled) or two LVCMOS Differential output swing is selectable: 400mV to 800mV Output Enable input with programmable effect 2 Supports up to 1MHz I C or up to 20MHz SPI serial processor port R31DS0043EU0110 Rev.1.1 Page 1 Jun.4.21RC22504A Datasheet Contents 1. About this Document 9 1.1 Document Conventions 9 1.1.1 Signal Notation . 9 1.1.2 Object Size Notation . 9 1.1.3 Numeric Notation 9 1.1.4 Endianness 9 2. Pin Information 10 2.1 Pin Assignments 10 2.2 Pin Descriptions 10 3. Specifications . 13 3.1 Absolute Maximum Ratings 13 3.2 Recommended Operating Conditions 13 3.3 Reference Clock Phase Jitter and Phase Noise 14 3.4 AC Electrical Characteristics . 16 3.5 DC Electrical Characteristics . 19 4. Applications Information 26 4.1 Power Considerations 26 4.2 Recommendations for Unused Input and Output Pins . 26 4.2.1 CLKIN/nCLKIN Input 26 4.2.2 LVCMOS Control Pins . 26 4.2.3 LVCMOS Outputs 26 4.2.4 Differential Outputs . 26 4.3 Clock Input Interface . 26 4.4 Crystal Recommendation . 27 4.5 Overdriving the XTAL Interface . 28 4.6 Differential Output Termination . 29 4.6.1 Direct-Coupled HCSL Termination 29 4.6.2 Direct-Coupled LVDS Termination 30 4.6.3 AC-Coupled Differential Termination 30 5. Architecture . 31 5.1 Modes of Operation 31 5.1.1 Frequency Synthesizer/Digitally Controlled Oscillator (DCO) . 31 5.1.2 Clock Generator 32 6. Blocks . 33 6.1 Device Reset Logic 33 6.1.1 Bias Calibration 33 6.2 Crystal Oscillator 33 6.3 Reference Clock Input 33 6.4 Analog Phase Lock Loop . 33 6.4.1 Frequency Doubler . 33 6.4.2 APLL Loop Filter (LPF) 34 6.4.3 Voltage-Controlled Oscillator (VCO) 34 6.4.4 APLL Feedback Divider 34 6.4.5 APLL Lock Detector . 34 6.4.6 Direct DCO Control . 34 R31DS0043EU0110 Rev.1.1 Page 2 Jun.4.21