Short Form Data Sheet April 2012 DS31400 8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter General Description Features The DS31400 is a flexible, high-performance timing IC Eight Input Clocks for diverse frequency conversion and frequency Differential or CMOS/TTL Format synthesis applications. On each of its eight input clocks Any Frequency from 2kHz to 750MHz and 14 output clocks, the device can accept or generate Fractional Scaling for 64B/66B and FEC Scaling nearly any frequency between 2kHz and 750MHz. The (e.g., 64/66, 237/255, 238/255) or Any Other device offers two independent DPLLs to serve two Downscaling Requirement independent clock-generation paths. Continuous Input Clock Quality Monitoring The input clocks are divided down, fractionally scaled as Automatic or Manual Clock Selection needed, and continuously monitored for activity and Three 2/4/8kHz Frame Sync Inputs frequency accuracy. The best input clock is selected, Two High-Performance DPLLs manually or automatically, as the reference clock for Hitless Reference Switching on Loss of Input each of the two flexible, high-performance digital PLLs. Automatic or Manual Phase Build-Out Each DPLL locks to the selected reference and provides Holdover on Loss of All Inputs programmable bandwidth, very high-resolution holdover Programmable Bandwidth, 0.5mHz to 400Hz capability, and truly hitless switching between input clocks. The digital PLLs are followed by a clock synthesis Seven Digital Frequency Synthesizers subsystem that has seven fully programmable digital Each Can Slave to Either DPLL frequency synthesis blocks, three high-speed low-jitter Produce Any 2kHz Multiple Up to 77.76MHz APLLs, and 14 output clocks, each with its own 32-bit Per-DFS Clock Phase Adjust divider and phase adjustment. The APLLs provide Three Output APLLs fractional scaling and output jitter less than 1ps RMS. Output Frequencies to 750MHz For telecom systems, the device has all required features High Resolution Fractional Scaling for FEC and and functions to serve as a central timing function or as a 64B/66B (e.g., 255/237, 255/238, 66/64) or Any line card timing IC. With a suitable oscillator the device Other Scaling Requirement meets the requirements of Stratum 2, 3E, 3, 4E, and 4 Less than 1ps RMS Output Jitter G.812 Types I to IV G.813 and G.8262. Simultaneously Produce Three Low-Jitter Rates from Applications the Same Reference (e.g., 622.08MHz for SONET, 255/237 x 622.08MHz for OTU2, and 156.25MHz for Frequency Conversion Applications in a Wide Variety of 10GE) Equipment Types 14 Output Clocks in Seven Groups Telecom Line Cards or Timing Cards with Any Mix of SONET/SDH, Synchronous Ethernet, and/or OTN Nearly Any Frequency from < 1Hz to 750MHz Ports in WAN Equipment Including MSPPs, Each Group Slaves to a DFS Clock, Any APLL Ethernet Switches, Routers, DSLAMs, and Base Clock, or Any Input Clock (Divided and Scaled) Stations Each Has a Differential Output (Three CML, Four LVDS/LVPECL) and Separate CMOS/TTL Ordering Information Output PART TEMP RANGE PIN-PACKAGE 32-Bit Frequency Divider Per Output DS31400GN 256 CSBGA Two Sync Pulse Outputs: 8kHz and 2kHz -40 C to +85 C General Features DS31400GN+ -40 C to +85 C 256 CSBGA Suitable Line Card IC or Timing Card IC for +Denotes a lead(Pb)-free/RoHS-compliant package. SPI is a trademark of Motorola, Inc. Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU Accepts and Produces Nearly Any Frequency fom 1Hz to 750MHz Internal Compensation for Local Oscillator Frequency Error SPI Processor Interface 1.8V Operation with 3.3V I/O (5V Tolerant) 17mm x 17mm CSGBA Package 1 Short Form Data Sheet DS31400 Application Example: Timing Card activity and frequency clock/data recovery, monitoring, select highest priority create derived DS1 or E1/2048kHz equalizer, framer, valid input for each DPLL clock locked to selected clock extract SSMs Timing Card (1 of 2) from BITS/SSU Backplane BITS Rx DS1, E1 or DS31400 2048 kHz to BITS/SSU N BITS APLL and DPLL1 <0> Tx divider Monitor, Divider, APLL, TCXO or Selector processor DPLL2 divider and OCXO fanout N typically 19.44MHz, Stratum 2, 3E or 3: 25MHz or 8kHz, jitter/wander filtering, point-to-point hitless switching, or multidrop buses N phase adjust, Timing Card (2 of 2) holdover <0> Identical to Timing Card 1 N <1> Line Card (1 of N) Line Card <1> Timing IC from port SERDES <1> (see Fig 2-2) to port SERDES <1> selects best system clock, best recovered line clock. hitless switching, frequency conversion, <N> jitter cleanup <N> Line Card (N of N) <N> <N> Application Example: Line Card clock monitoring and selection, hitless switching, holdover, frequency conversion, fractional scaling, jitter attenuation 19.44MHz, 38.88MHz, 25MHz, etc. DS31400 IC1 system timing n OC1 to OC5 clocks to line card SERDES DPLL1 Path from master and slave SONET/SDH, 1GE, 10GE, OTN, FC, etc. IC2 timing cards 3 unrelated frequencies simultaneously at <1ps rms jitter plus other frequencies at somewhat higher jitter OC6 line timing recovered line clocks from SERDES IC3 to IC8 n SONET/SDH, 1GE, 10GE, OTN, FC etc. DPLL2 Path to master and slave OC7 frequencies can be unrelated to one another timing cards 8kHz, 19.44MHz, 155.52M, 622.08M, 25M, 38.88MHz, 25MHz, etc. 125M, 156.25M, etc. with or without fractional scaling for clock monitoring and selection, FEC, 64B/66B, etc. undo fractional scaling, MANY other rates possible, frequency conversion including DS1, E1, DS3, E3, 10M and Nx19.44M. 2