BUJ105AB,118 NXP

DISCRETE SEMICONDUCTORS DATA SHEET BUJ105AB Silicon Diffused Power Transistor Product specification October 2018WeEn Semiconductors Product specification Silicon Diffused Power Transistor BUJ105AB GENERAL DESCRIPTION 2 High-voltage, high-speed planar-passivated npn power switching transistor in SOT404 (D -PAK) surface-mount package intended for use in high frequency electronic lighting ballast applications, converters, inverters, switching regulators, motor control systems, etc. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT V Collector-emitter voltage peak value V = 0 V - 700 V CESM BE V Collector-Base voltage (open emitter) - 700 V CBO V Collector-emitter voltage (open base) - 400 V CEO I Collector current (DC) - 8 A C I Collector current peak value - 16 A CM P Total power dissipation T 25 C - 125 W tot mb V Collector-emitter saturation voltage I = 4.0 A I = 0.8 A 0.3 1.0 V CEsat C B h I = 4.0 A V = 5 V 11 15 FEsat C CE t Fall time I = 5 A I = 1 A 20 50 ns f C B1 PINNING - SOT404 PIN CONFIGURATION SYMBOL PIN DESCRIPTION mb 1 base 2 collector 2 3 emitter 1 3 mb collector D2PAK (SOT404) LIMITING VALUES Limiting values in accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V Collector to emitter voltage V = 0 V - 700 V CESM BE V Collector to emitter voltage (open base) - 400 V CEO V Collector to base voltage (open emitter) - 700 V CBO I Collector current (DC) - 8 A C I Collector current peak value - 16 A CM I Base current (DC) - 4 A B I Base current peak value - 8 A BM P Total power dissipation T 25 C - 125 W tot mb T Storage temperature -65 150 C stg T Junction temperature - 150 C j THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT R Thermal resistance junction to mounting - 1.0 K/W th j-mb base R Thermal resistance junction to ambient minimum footprint, FR4 board 55 - K/W th j-a October 2018 1 Rev 1.100