XTAL IN FemtoClocksCrystal-TO-LVDS 844002-01 Frequency Synthesizer DATA SHEET Description Features The 844002-01 is a 2 output LVDS Synthesizer optimized to Two differential LVDS outputs generate Ethernet reference clock frequencies. Using a 25MHz, Selectable crystal oscillator interface or 18pF parallel resonant crystal, the following frequencies can be single-ended LVCMOS/LVTTL input generated based on the 2 frequency select pins (F SEL 1:0 ): Supports the following output frequencies: 156.25MHz, 156.25MHz, 125MHz and 62.5MHz. The 844002-01 uses IDTs 125MHz, 62.5MHz rd 3 generation low phase noise VCO technology and can achieve VCO range: 560MHz 680MHz <1ps typical rms phase jitter, easily meeting Ethernet jitter RMS phase jitter 156.25MHz, using a 25MHz crystal requirements. The 844002-01 is packaged in a small 20-pin (1.875MHz 20MHz): 0.41ps (typical) TSSOP package. Full 3.3V and 2.5V supply modes 0C to 70C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Pulldown 2 nc 1 20 VDDO F SEL 1:0 VDDO 2 19 Q1 Pulldown PLL SEL Q0 3 18 Q1 Q0 Q0 4 17 GND F SEL 1:0 Q0 MR 5 16 nc Pulldown 0 0 4 REF CLK 11 PLL SEL 6 15 XTAL SEL 1 0 1 5 nc 7 14 REF CLK 25MHz 1 0 10 VDDA 8 13 VCO XTAL IN 1 1 not used Phase Q1 F SEL0 9 12 XTAL OUT 625MHz 0 OSC 0 Detector (w/25MHz VDD 10 11 F SEL1 Reference) Q1 XTAL OUT 844002-01 Pulldown XTAL SEL 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm M = 25 (fixed) package body G Package Top View Pulldown MR 844002-01 Rev A 6/9/15 1 2015 Integrated Device Technology, Inc.844002-01 DATA SHEET Table 1. Pin Descriptions Number Name Type Description 1, 7 nc Unused No connect. 2, 20 V Power Output supply pins. DDO 3, 4 Q0, Q0 Output Differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs Qx to go high. 5 MR Input Pulldown When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and REF CLK as input to the dividers. When LOW, 6 PLL SEL Input Pulldown selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. Power Analog supply pin. 8V DDA 9, FSEL0, Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. 11 F SEL1 10 V Power Core supply pins. DD 12, XTAL OUT Parallel resonant crystal interface. XTAL OUT is the output, , Input 13 XTAL IN XTAL IN is the input. 14 REF CLK Input Pulldown Non-inverting differential clock input. Selects between crystal or REF CLK inputs as the PLL Reference source. Input Pulldown Selects XTAL inputs when LOW. Selects REF CLK when HIGH. 15 XTAL SEL LVCMOS/LVTTL interface levels. 16 nc Unused No connect. 17 GND Power Power supply ground. 18, 19 Q1, Q1 Output Differential output pair. LVDS interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN Input Pulldown Resistor 51 k R PULLDOWN FEMTOCLOCKSCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER 2 Rev A 6/9/15