CTLDM7120-M621H
SURFACE MOUNT
www.centralsemi.com
N-CHANNEL
DESCRIPTION:
ENHANCEMENT-MODE
The CENTRAL SEMICONDUCTOR CTLDM7120-M621H is
SILICON MOSFET
an Enhancement-mode N-Channel Field Effect Transistor,
manufactured by the N-Channel DMOS Process, designed
for high speed pulsed amplifier and driver applications.
This MOSFET offers Low r and Low Threshold
DS(ON)
Voltage.
MARKING CODE: CNH
TLM621H CASE
Device is Halogen Free by design
FEATURES:
APPLICATIONS: ESD protection up to 2kV
Load/Power switches Low r (0.25 MAX @ V =1.5V)
DS(ON) GS
Power supply converter circuits High current (I =1.0A)
D
Battery powered portable equipment Logic level compatibility
MAXIMUM RATINGS: (T =25C) SYMBOL UNITS
A
Drain-Source Voltage V 20 V
DS
Gate-Source Voltage V 8.0 V
GS
Continuous Drain Current (Steady State) I 1.0 A
D
Maximum Pulsed Drain Current, tp=10s I 4.0 A
DM
Power Dissipation (Note 1) P 1.6 W
D
Operating and Storage Junction Temperature T T -65 to +150 C
J, stg
Thermal Resistance (Note 1) 75 C/W
JA
ELECTRICAL CHARACTERISTICS: (T =25C unless otherwise noted)
A
SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
I , I V =8.0V, V=0 10 A
GSSF GSSR GS DS
I V =20V, V=0 10 A
DSS DS GS
BV V =0, I=250A 20 V
DSS GS D
V V =10V, I=1.0mA 0.5 1.2 V
GS(th) DS D
V V =0, I=1.0A 1.1 V
SD GS S
r V =4.5V, I=0.5A 0.075 0.10
DS(ON) GS D
r V =2.5V, I=0.5A 0.10 0.14
DS(ON) GS D
r V =1.5V, I=0.1A 0.17 0.25
DS(ON) GS D
Q V =10V, V =4.5V, I=1.0A 2.4 nC
g(tot) DS GS D
Q V =10V, V =4.5V, I=1.0A 0.25 nC
gs DS GS D
Q V =10V, V =4.5V, I=1.0A 0.65 nC
gd DS GS D
g V =10V, I=0.5A 4.2 S
FS DS D
C V =10V, V =0, f=1.0MHz 45 pF
rss DS GS
C V =10V, V =0, f=1.0MHz 220 pF
iss DS GS
C V =10V, V =0, f=1.0MHz 120 pF
oss DS GS
t V =10V, V =5.0V, I=0.5A 25 ns
on DD GS D
t V =10V, V =5.0V, I =0.5A 140 ns
off DD GS D
Notes: (1) Mounted on a 4-layer JEDEC test board with one thermal vias connecting the
exposed thermal pad to the first buried plane. PCB was constructed as per
R3 (2-August 2011)
JEDEC standards JESD51-5 and JESD51-7.CTLDM7120-M621H
SURFACE MOUNT
N-CHANNEL
ENHANCEMENT-MODE
SILICON MOSFET
TLM621H CASE - MECHANICAL OUTLINE
OPTIONAL MOUNTING PADS
(Dimensions in mm)
For standard mounting refer
*Exposed pad P internally connected to pins 2, 3, 4, and 5.
to TLM621H Package Details
PIN CONFIGURATION
LEAD CODE:
1) Source
2) Drain
3) Drain
4) Drain
5) Drain
6) Gate
MARKING CODE: CNH
R3 (2-August 2011)
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